Silicon wafers used in MOS ULSI devices are almost all grown via Czochralski (CZ) crystal pulling method. Silicon single crystals grown via this CZ process ordinarily contain around 10.sup.18 atoms/cm.sup.3 of oxygen impurities, and if used as-is in device fabrication processes, the supersaturated oxygen atoms precipitate during processing.
Further, the volume expansion of this oxygen precipitate causes secondary defects such as dislocations and stacking faults. These oxygen precipitates (BMD) and their secondary defects greatly impact the characteristics of a semiconductor device, and when defect occurs on the wafer surface or in the device active layer, it causes increases in leakage current and poor gate oxide integrity (GOI).
Further, grown-in defects introduced during the growth of silicon single crystal using the CZ process were not considered problems in line with the increased integration and downscaling of metal oxide semiconductor (MOS) large scale integration (LSI) up to the 16 megabit dynamic random access memory (16M DRAM) stage. However, because it markedly degrades the GOI characteristics of an MOS capacitor, for 64M DRAM and subsequent devices, the suitability of the near-surface crystallinity of a silicon single crystal substrate will be a major factor in determining device reliability and yield.
Therefore, as a method of improving GOI characteristics during the growth of single crystals via the CZ process, it has been proposed (Kokai No. 2-267195) that a crystal growth rate wherein a crystal is pulled at a slow speed of less than 0.8 mm/min can greatly improve the GOI characteristics of a silicon single crystal substrate.
Further, as a method for reducing grown-in defect in silicon single crystals, it has been proposed (Kokai No. 8-12493) that crystal growth be carried out by setting the cooling rate in the temperature range between 1,150.degree. C. and 1,000.degree. C. to less than 2.0.degree. C./min.
As a separate procedure, it was disclosed in Kokai No. 5-319987 and Kokai No. 5-319988 that grown-in defect introduced during crystal growth can be shrunk and eliminated, and the reliability of a gate oxide layer can be improved by annealing a silicon single crystal ingot at between 1,150.degree. C. and 1,400.degree. C. immediately after it has been pulled via the CZ process.
Further, as a means of wafer annealing, Kokai No. 60-231365, Kokai No. 61-193456, and Kokai No. 61-193458 and others disclosed a method for forming a DZ layer by promoting the outward diffusion of oxygen near a silicon wafer surface layer by annealing a silicon substrate for 5 minutes or longer at temperatures ranging from 950.degree. C. and 1,200.degree. C. in a hydrogen environment or a hydrogen-containing environment.
Meanwhile, heavy metal contaminants typified by iron (Fe), nickel (Ni) and copper (Cu) occur in a high-temperature annealing process in the processing of an ultra large scale integration (ULSI) device. When these heavy metal contaminants cause the formation of wafer near-surface defects and deep level in forbidden band, which degrades a carrier lifetime, device characteristics deteriorate. It is therefore necessary to remove these heavy metal contaminants from the wafer near-surface, a task that has been accomplished for some time now using IG and various extrinsic gettering (EG) procedures.
It is clear that device processing in the future will achieve yet higher levels of integration and lower the temperature of processes that use high energy ion implants. When this happens, it is predicted that the growth of BMD during processing will become difficult in low temperature processes. Therefore, it will be difficult to achieve the same adequate IG effects with low temperature processes as are possible with high temperature processes. Further, even if processing temperatures are lowered, it will be difficult to avoid heavy metal contaminants such as those in high-energy ion implant processes, thus making gettering technology imperative.
Up until now, DZ-IG processing has been widely used to heighten the quality surface active region of silicon wafers grown using an ordinary CZ process. As explained above, this method reduces interstitial oxygen,which comprises the core of a micro-defect, and forms a oxygen precipitate-free denuded zone (DZ) layer in the device active region by outwardly diffusing oxygen in the wafer near-surface by subjected the wafer to high-temperature processing at temperatures ranging between 1,100.degree. C. and 1,200.degree. C. Thereafter, low-temperature annealing is performed at between 600.degree. C. and 900.degree. C. in order to form oxygen precipitate nuclei in the wafer bulk.
However, as a method for improving GOI characteristics during growth of a single crystal via the CZ process, the above-described method of slowing down the crystal growth rate to less than 0.8 mm/min greatly lowers productivity by slowing down the crystal pulling rate. Another problem with this method is that it produces a crystal that is rich in interstitial silicon atoms, and generates a dislocation loop attributable to excess interstitial silicon atoms. On the other hand, it is also impossible to eliminate grown-in defect by lowering the cooling rate in the temperature range from 1,150.about.1,000.degree. C. to less than 2.0.degree. C./min when pulling a silicon single crystal.
The method for annealing a silicon ingot directly at a temperature higher than 1,150.degree. C. but lower than 1,400.degree. C. generates dislocation and slip throughout the ingot, rendering the product unusable. On the other hand, although the method of annealing a silicon wafer at between 900.degree. C. and 1,200.degree. C. in a hydrogen environment or hydrogen-containing environment certainly eliminates grown-in defects on the surface or near-surface silicon regions to a depth of about 2 .mu.m, the need to once again mirror polish the wafer surface to remove the particles that adhere to the wafer surface during the annealing process, and the surface scratches resulting from wafer transport, drastically reduces the effects of that annealing method
DRAM devices with trench capacitors can not expect enhancing device characteristics at all, since the trench capacitors extend to about 8.about.10 .mu.m depth from the surface and the existence of grown-in defect causes leakage current.
Furthermore, wafer annealing is generally done either in a horizontal or vertical furnace, and the wafers undergoing annealing are placed one-wafer-per-slot in a boat made of either silicon carbide (SiC) or quartz, making it difficult to process large numbers of wafers at the same time.
Accordingly, a method for annealing large numbers of silicon single crystal wafers and the equipment therefor have been disclosed in Kokai No. 57-97622 and Kokai No. 53-25351, and are depicted in FIG. 18.
This configuration calls for placing a plurality of silicon single crystal wafers 1 one beside the other transversely in a perpendicular state inside a silicon boat 2, supporting this stack of silicon single crystal wafers 1 by pressure applied via backslides 3 at both ends of the stack, and heat processing the supported silicon single crystal wafers 1 in this silicon boat 2 inside an annealing furnace 4. Since the backslides 3 maintain even pressure from both ends on all of the plurality of silicon single crystal wafers 1 lined up transversely like this, it is possible to diffuse high concentrations of impurities deep within the wafers with little warpage and slight variations in diffusion depth and surface concentrations.
Generally, when a slip dislocation occurs in a silicon wafer, devices fabricated on that silicon substrate are adversely affected by increased leakage current generated from the slip dislocation, and can not stand up to practical use. With the annealing equipment depicted in FIG. 18, silicon single crystal wafers 1 are lined up side-by-side transversely in a silicon boat 2, and since the edges of these silicon single crystal wafers 1 come in contact with the silicon boat 2, there has been a problem of slip dislocation formation occurring during annealing at all the contact points of all the stacked silicon single crystal wafers 1. This equipment has not yet been used in actual production operations.
As explained above, there is no method for completely eliminating grown-in defect induced during CZ crystal pulling. As a countermeasure, there is a strong movement in support of growing silicon epitaxially on the surface of CZ-grown silicon wafers. This epitaxial layer exhibits extremely good GOI characteristics. But there are numerous drawbacks to this approach. First of all, epi wafers imply high manufacturing cost. SiHCl.sub.3 and SiH.sub.2 Cl.sub.2 are used as the silicon source materials, and HCl gas is used in the wafer cleaning process. The chlorine atoms therein promote the corrosion of piping, facilitate the generation of heavy metal contaminants.
The nature of the grown-in defects in a octahedral void defect surrounded by (111) surface with a few nm oxide film, as shown in FIG. 17B. When the grown-in defects are exposed on the surface in following wafer shaping processes, as shown in FIG. 17A, quadrangular pyramid-shaped concave pits with a diameter of between 0.1.about.0.2 .mu.m, so called COP (crystal originated particle), appear and have adversely affected GOI characteristics. However, in the past, no matter what conventional annealing method was used, it was impossible to reduce grown-in defects from surface active region.